commit f2a3aae4ac4d914d9fb8587ee7d1a7756bbc66c3
author Brian Smith <brian@briansmith.org> Tue Dec 05 19:00:21 2023 -0800
committer Boringssl LUCI CQ <boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com> Tue Dec 12 16:22:37 2023 +0000
tree 1a58fb8db55e4a43ae4588c1546f3b0622a89242
parent 9e40481d5bfe08e3e6daa5335c2cf076e1187ec1

sha: Remove check for SSSE3 for AVX variants.

I verified using Intel XED that all the non-base instructions are
classified as AVX for the _avx variants or AVX/AVX2/BMI/BMI2 for
sha1_block_data_order_avx2.

Change-Id: Id0b744369ff81521d33230bf337e4dff963aecd4
Reviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/64547
Reviewed-by: David Benjamin <davidben@google.com>
Commit-Queue: Bob Beck <bbe@google.com>
Reviewed-by: Bob Beck <bbe@google.com>

crypto/fipsmodule/sha/internal.h

diff --git a/crypto/fipsmodule/sha/internal.h b/crypto/fipsmodule/sha/internal.h
index 7dbab6b..28975e1 100644
--- a/crypto/fipsmodule/sha/internal.h
+++ b/crypto/fipsmodule/sha/internal.h
@@ -73,24 +73,17 @@
 
 #define SHA1_ASM_AVX2
 OPENSSL_INLINE int sha1_avx2_capable(void) {
-  // TODO: Simplify this logic, which was extracted from the assembly:
-  //  * Does AVX2 imply SSSE3?
-  //  * sha1_block_data_order_avx2 does not seem to use SSSE3 instructions.
   return CRYPTO_is_AVX2_capable() && CRYPTO_is_BMI2_capable() &&
-         CRYPTO_is_BMI1_capable() && CRYPTO_is_SSSE3_capable();
+         CRYPTO_is_BMI1_capable();
 }
 void sha1_block_data_order_avx2(uint32_t *state, const uint8_t *data,
                                 size_t num);
 
 #define SHA1_ASM_AVX
 OPENSSL_INLINE int sha1_avx_capable(void) {
-  // TODO: Simplify this logic, which was extracted from the assembly:
-  //  * Does AVX imply SSSE3?
-  //  * sha1_block_data_order_avx does not seem to use SSSE3 instructions.
   // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
   // discussion in sha1-586.pl.
-  return CRYPTO_is_AVX_capable() && CRYPTO_is_SSSE3_capable() &&
-         CRYPTO_is_intel_cpu();
+  return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
 }
 void sha1_block_data_order_avx(uint32_t *state, const uint8_t *data,
                                size_t num);
@@ -109,13 +102,9 @@
 
 #define SHA256_ASM_AVX
 OPENSSL_INLINE int sha256_avx_capable(void) {
-  // TODO: Simplify this logic, which was extracted from the assembly:
-  //  * Does AVX imply SSSE3?
-  //  * sha256_block_data_order_avx does not seem to use SSSE3 instructions.
   // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
   // discussion in sha1-586.pl.
-  return CRYPTO_is_AVX_capable() && CRYPTO_is_SSSE3_capable() &&
-         CRYPTO_is_intel_cpu();
+  return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
 }
 void sha256_block_data_order_avx(uint32_t *state, const uint8_t *data,
                                  size_t num);
@@ -129,13 +118,9 @@
 
 #define SHA512_ASM_AVX
 OPENSSL_INLINE int sha512_avx_capable(void) {
-  // TODO: Simplify this logic, which was extracted from the assembly:
-  //  * Does AVX imply SSSE3?
-  //  * sha512_block_data_order_avx does not seem to use SSSE3 instructions.
   // Pre-Zen AMD CPUs had slow SHLD/SHRD; Zen added the SHA extension; see the
   // discussion in sha1-586.pl.
-  return CRYPTO_is_AVX_capable() && CRYPTO_is_SSSE3_capable() &&
-         CRYPTO_is_intel_cpu();
+  return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
 }
 void sha512_block_data_order_avx(uint64_t *state, const uint8_t *data,
                                  size_t num);