|author||Adam Langley <email@example.com>||Wed Jan 16 17:20:24 2019 -0800|
|committer||Adam Langley <firstname.lastname@example.org>||Mon Jan 21 21:32:35 2019 +0000|
Simplify HRSS mod3 circuits. The multiplication and subtraction circuits were found by djb using GNU Superoptimizer, and the addition circuit is derived from the subtraction one by hand. They depend on a different representation: -1 is now (1, 1) rather than (1, 0), and the latter becomes undefined. The following Python program checks that the circuits work: values = [0, 1, -1] def toBits(v): if v == 0: return 0, 0 elif v == 1: return 0, 1 elif v == -1: return 1, 1 else: raise ValueError(v) def mul((s1, a1), (s2, a2)): return ((s1 ^ s2) & a1 & a2, a1 & a2) def add((s1, a1), (s2, a2)): t = s1 ^ a2 return (t & (s2 ^ a1), (a1 ^ a2) | (t ^ s2)) def sub((s1, a1), (s2, a2)): t = a1 ^ a2 return ((s1 ^ a2) & (t ^ s2), t | (s1 ^ s2)) def fromBits((s, a)): if s == 0 and a == 0: return 0 if s == 0 and a == 1: return 1 if s == 1 and a == 1: return -1 else: raise ValueError((s, a)) def wrap(v): if v == 2: return -1 elif v == -2: return 1 else: return v for v1 in values: for v2 in values: print v1, v2 result = fromBits(mul(toBits(v1), toBits(v2))) if result != v1 * v2: raise ValueError((v1, v2, result)) result = fromBits(add(toBits(v1), toBits(v2))) if result != wrap(v1 + v2): raise ValueError((v1, v2, result)) result = fromBits(sub(toBits(v1), toBits(v2))) if result != wrap(v1 - v2): raise ValueError((v1, v2, result)) Change-Id: Ie1a4ca5a82c2651057efc62330eca6fdd9878122 Reviewed-on: https://boringssl-review.googlesource.com/c/34344 Reviewed-by: David Benjamin <email@example.com>
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