)]}'
{
  "commit": "d8beaa340640f8742b81721cc756309f69ecd579",
  "tree": "2648865cbedc9c56ef9e2b7bdeba4b02c9577eca",
  "parents": [
    "b803ed04706c772335abce3fb8b2c1cc43ca2cd4"
  ],
  "author": {
    "name": "Eric Biggers",
    "email": "ebiggers@google.com",
    "time": "Mon Mar 10 10:27:59 2025 -0700"
  },
  "committer": {
    "name": "Boringssl LUCI CQ",
    "email": "boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Mon Mar 10 15:04:25 2025 -0700"
  },
  "message": "Fix missing vzeroupper in gcm_ghash_vpclmulqdq_avx2() for len\u003d16\n\ngcm_ghash_vpclmulqdq_avx2() executes vzeroupper only when len \u003e\u003d 32, as\nit was supposed to use only xmm registers for len \u003d\u003d 16.  But actually\nit was writing to two ymm registers unconditionally for $BSWAP_MASK and\n$GFPOLY.  Therefore, there could be a slow-down in later code using\nlegacy SSE instructions, in the (probably rare) case where\ngcm_ghash_vpclmulqdq_avx2() was called with len\u003d16 *and* wasn\u0027t followed\nby a function that does vzeroupper, e.g. aes_gcm_enc_update_vaes_avx2().\n\n(The Windows xmm register restore epilogue of\ngcm_ghash_vpclmulqdq_avx2() itself does use legacy SSE instructions, so\nprobably was slowed down by this, but that\u0027s just 8 instructions.)\n\nFix this by updating gcm_ghash_vpclmulqdq_avx2() to correctly use only\nxmm registers when len\u003d16.  This makes it match the similar code in\naes-gcm-avx10-x86_64.pl, which does do it correctly, more closely.\n\nAlso, make both functions just execute vzeroupper unconditionally, so\nthat it won\u0027t be missed again.  It\u0027s actually only 1 cycle on the CPUs\nthis code runs on, and it no longer seems worth executing conditionally.\n\nChange-Id: I975cd5b526e5cdae1a567f4085c2484552bf6bea\nReviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/77227\nReviewed-by: David Benjamin \u003cdavidben@google.com\u003e\nCommit-Queue: David Benjamin \u003cdavidben@google.com\u003e\n",
  "tree_diff": [
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