)]}'
{
  "commit": "c98b28bd5e99a0983de8389435621df1e04d1e62",
  "tree": "bbaa3c3ba8baae6aa1253fa37e56feb2acd5c763",
  "parents": [
    "08a232f5766a5bd575eab5939578f6aaf5c414d3"
  ],
  "author": {
    "name": "Eric Biggers",
    "email": "ebiggers@google.com",
    "time": "Wed Aug 14 16:40:38 2024 +0000"
  },
  "committer": {
    "name": "Boringssl LUCI CQ",
    "email": "boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Wed Aug 14 21:44:37 2024 +0000"
  },
  "message": "Clear AVX512 feature bits when AVX512 not actually supported\n\nAccording to Intel\u0027s documentation, if not all the AVX512 bits in XCR0\nare set (meaning that the operating system doesn\u0027t fully support\nAVX512), then no AVX512 feature can be used, even on xmm and ymm\nregisters.  Make OPENSSL_cpuid_setup() correctly handle this case by\nclearing all the AVX512 feature bits when this situation is detected.\n\nChange-Id: I2774dbc28bfbac1196e405c0920ba2909e7f0eb3\nReviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/68907\nReviewed-by: David Benjamin \u003cdavidben@google.com\u003e\nReviewed-by: Bob Beck \u003cbbe@google.com\u003e\nCommit-Queue: Adam Langley \u003cagl@google.com\u003e\nAuto-Submit: Eric Biggers \u003cebiggers@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "347eadca988701e407ef52df7b228fa4b3c93293",
      "old_mode": 33188,
      "old_path": "crypto/cpu_intel.c",
      "new_id": "3453fa39145e2efdab1b3d83a8dd819f19788093",
      "new_mode": 33188,
      "new_path": "crypto/cpu_intel.c"
    },
    {
      "type": "modify",
      "old_id": "89d1e80e911ee15b1b10ca3049fcfcf4b191c22e",
      "old_mode": 33188,
      "old_path": "crypto/internal.h",
      "new_id": "209c85a34dc8aabd4beb9176bc57d266483933fe",
      "new_mode": 33188,
      "new_path": "crypto/internal.h"
    }
  ]
}