| commit | b1e6a85443ccaf47c6a2c11b18b090bb0f97eea0 | [log] [tgz] |
|---|---|---|
| author | Jesse Selover <jselover@google.com> | Thu Apr 19 16:34:35 2018 -0400 |
| committer | CQ bot account: commit-bot@chromium.org <commit-bot@chromium.org> | Thu Apr 19 20:48:58 2018 +0000 |
| tree | 654268188692937d79c4a6bbda0783b35a8529ca | |
| parent | 35e7c994bede902847642b1d319780975a66061b [diff] [blame] |
Change OPENSSL_cpuid_setup to reserve more extended feature space. Copy of openssl change https://git.openssl.org/gitweb/?p=openssl.git;h=d6ee8f3dc4414cd97bd63b801f8644f0ff8a1f17 OPENSSL_ia32cap: reserve for new extensions. Change-Id: I96b43c82ba6568bae848449972d3ad9d20f6d063 Reviewed-on: https://boringssl-review.googlesource.com/27564 Reviewed-by: David Benjamin <davidben@google.com> Reviewed-by: Steven Valdez <svaldez@google.com> Commit-Queue: David Benjamin <davidben@google.com> CQ-Verified: CQ bot account: commit-bot@chromium.org <commit-bot@chromium.org>
diff --git a/include/openssl/cpu.h b/include/openssl/cpu.h index dd95ddc..bb847f9 100644 --- a/include/openssl/cpu.h +++ b/include/openssl/cpu.h
@@ -86,7 +86,8 @@ // Bit 11 is used to indicate AMD XOP support, not SDBG // Index 2: // EBX for CPUID where EAX = 7 -// Index 3 is set to zero. +// Index 3: +// ECX for CPUID where EAX = 7 // // Note: the CPUID bits are pre-adjusted for the OSXSAVE bit and the YMM and XMM // bits in XCR0, so it is not necessary to check those.