)]}'
{
  "commit": "afaccd42b9804b0aaa1754e85ca2b4961cd95a27",
  "tree": "9908934784d3e85d04fdacf8972813e565fae21c",
  "parents": [
    "2d94b5e1ee99a22c2fd3bb3b3dd5b4e3be6b3cc6"
  ],
  "author": {
    "name": "Eric Biggers",
    "email": "ebiggers@google.com",
    "time": "Tue Aug 20 23:24:15 2024 +0000"
  },
  "committer": {
    "name": "Boringssl LUCI CQ",
    "email": "boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Wed Aug 28 19:49:59 2024 +0000"
  },
  "message": "Support detecting preference for ymm registers over zmm\n\nAdd a CPU capability bit that identifies older Intel CPUs that support\nAVX512 but where using zmm registers should be avoided.  This will be\nused to select code that uses ymm registers instead.\n\nChange-Id: I6bedc913960d0da3c5f3aae315c81f67da1667b4\nReviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/68909\nReviewed-by: David Benjamin \u003cdavidben@google.com\u003e\nReviewed-by: Bob Beck \u003cbbe@google.com\u003e\nCommit-Queue: Bob Beck \u003cbbe@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "10e7871e43235f41a53d78073f1e747fa0bb529a",
      "old_mode": 33188,
      "old_path": "crypto/cpu_intel.c",
      "new_id": "71934935cb1c436816b0864d9042e08f09da9dde",
      "new_mode": 33188,
      "new_path": "crypto/cpu_intel.c"
    },
    {
      "type": "modify",
      "old_id": "4ec12f563be1b3e709150585d20aa45b5372ab3c",
      "old_mode": 33188,
      "old_path": "crypto/internal.h",
      "new_id": "5ca29ae2a021f3d3e5bc9b1e7c8bee1899e80089",
      "new_mode": 33188,
      "new_path": "crypto/internal.h"
    }
  ]
}