Stop checking the FXSR bit
We assume SSE2 as a baseline, so this should all be moot. See also the
discussion at https://crbug.com/42290563
Fixed: 42290563
Change-Id: I05e7f9feca3133debc29ec3d16e749252e01fcdb
Reviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/76148
Commit-Queue: David Benjamin <davidben@google.com>
Reviewed-by: Bob Beck <bbe@google.com>
Auto-Submit: David Benjamin <davidben@google.com>
Reviewed-by: Adam Langley <agl@google.com>
Commit-Queue: Adam Langley <agl@google.com>
Commit-Queue: Bob Beck <bbe@google.com>
diff --git a/crypto/chacha/internal.h b/crypto/chacha/internal.h
index 828621b..9abf6b5 100644
--- a/crypto/chacha/internal.h
+++ b/crypto/chacha/internal.h
@@ -37,7 +37,7 @@
inline int ChaCha20_ctr32_ssse3_capable(size_t len) {
// Unlike the x86_64 version, the x86 SSSE3 routine runs for all non-zero
// lengths.
- return len > 0 && CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
+ return len > 0 && CRYPTO_is_SSSE3_capable();
}
void ChaCha20_ctr32_ssse3(uint8_t *out, const uint8_t *in, size_t in_len,
const uint32_t key[8], const uint32_t counter[4]);
diff --git a/crypto/fipsmodule/aes/gcm.cc.inc b/crypto/fipsmodule/aes/gcm.cc.inc
index c3c68f2..87ef5b8 100644
--- a/crypto/fipsmodule/aes/gcm.cc.inc
+++ b/crypto/fipsmodule/aes/gcm.cc.inc
@@ -596,7 +596,7 @@
#if defined(OPENSSL_X86) || defined(OPENSSL_X86_64)
int crypto_gcm_clmul_enabled(void) {
#if defined(GHASH_ASM_X86) || defined(GHASH_ASM_X86_64)
- return CRYPTO_is_FXSR_capable() && CRYPTO_is_PCLMUL_capable();
+ return CRYPTO_is_PCLMUL_capable();
#else
return 0;
#endif
diff --git a/crypto/fipsmodule/sha/internal.h b/crypto/fipsmodule/sha/internal.h
index 7a6007c..bd29719 100644
--- a/crypto/fipsmodule/sha/internal.h
+++ b/crypto/fipsmodule/sha/internal.h
@@ -74,9 +74,7 @@
#define SHA1_ASM_SSSE3
inline int sha1_ssse3_capable(void) {
- // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
- // say to.
- return CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
+ return CRYPTO_is_SSSE3_capable();
}
void sha1_block_data_order_ssse3(uint32_t state[5], const uint8_t *data,
size_t num);
@@ -86,19 +84,14 @@
// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl.
//
// TODO(crbug.com/42290564): Should we enable SHAEXT on 32-bit x86?
- // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
- // say to.
- return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu() &&
- CRYPTO_is_FXSR_capable();
+ return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
}
void sha1_block_data_order_avx(uint32_t state[5], const uint8_t *data,
size_t num);
#define SHA256_ASM_SSSE3
inline int sha256_ssse3_capable(void) {
- // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
- // say to.
- return CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
+ return CRYPTO_is_SSSE3_capable();
}
void sha256_block_data_order_ssse3(uint32_t state[8], const uint8_t *data,
size_t num);
@@ -108,19 +101,14 @@
// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl.
//
// TODO(crbug.com/42290564): Should we enable SHAEXT on 32-bit x86?
- // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
- // say to.
- return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu() &&
- CRYPTO_is_FXSR_capable();
+ return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
}
void sha256_block_data_order_avx(uint32_t state[8], const uint8_t *data,
size_t num);
#define SHA512_ASM_SSSE3
inline int sha512_ssse3_capable(void) {
- // TODO(davidben): Do we need to check the FXSR bit? The Intel manual does not
- // say to.
- return CRYPTO_is_SSSE3_capable() && CRYPTO_is_FXSR_capable();
+ return CRYPTO_is_SSSE3_capable();
}
void sha512_block_data_order_ssse3(uint64_t state[8], const uint8_t *data,
size_t num);
diff --git a/crypto/internal.h b/crypto/internal.h
index 1a23bec..c41fa1b 100644
--- a/crypto/internal.h
+++ b/crypto/internal.h
@@ -1118,14 +1118,6 @@
// See Intel manual, volume 2A, table 3-11.
-inline int CRYPTO_is_FXSR_capable(void) {
-#if defined(__FXSR__)
- return 1;
-#else
- return (OPENSSL_get_ia32cap(0) & (1u << 24)) != 0;
-#endif
-}
-
inline int CRYPTO_is_intel_cpu(void) {
// The reserved bit 30 is used to indicate an Intel CPU.
return (OPENSSL_get_ia32cap(0) & (1u << 30)) != 0;
