commit 770033594cfd4a48ed6045e256826c67aa3d90b6
author David Benjamin <davidben@google.com> Mon Feb 03 16:35:49 2025 -0500
committer Boringssl LUCI CQ <boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com> Tue Feb 04 13:14:28 2025 -0800
tree edf6a12a005bb4dccbfcd124861f2094e3ac94ea
parent 9a8c72d91959f68fe86291b5d07557a7f1cee906

Remove now unnecessary ia32cap_P customizations

Now that we have no assembly references, we only need the customizations
that the wrapper functions in crypto/internal.h consume.

I considered adding little breadcrumbs in comments, but it's very, very
unlikely that they'll come up in some future assembly that we import.
We're not adding new RC4 optimizations, AMD XOP is only going to be
become less relevant, and weakening the constant-time model for
non-hyperthreaded x86 cores is probably the least relevant of all of
these.

Bug: 42290548
Change-Id: I08b9681ac38343889e3687e547c19cd2d4681912
Reviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/75868
Auto-Submit: David Benjamin <davidben@google.com>
Commit-Queue: David Benjamin <davidben@google.com>
Reviewed-by: Bob Beck <bbe@google.com>

crypto/cpu_intel.cc

diff --git a/crypto/cpu_intel.cc b/crypto/cpu_intel.cc
index 6386df0..05acad2 100644
--- a/crypto/cpu_intel.cc
+++ b/crypto/cpu_intel.cc
@@ -171,14 +171,6 @@
     }
   }
 
-  // Force the hyper-threading bit so that the more conservative path is always
-  // chosen.
-  edx |= 1u << 28;
-
-  // Reserved bit #20 was historically repurposed to control the in-memory
-  // representation of RC4 state. Always set it to zero.
-  edx &= ~(1u << 20);
-
   // Reserved bit #30 is repurposed to signal an Intel CPU.
   if (is_intel) {
     edx |= (1u << 30);
@@ -186,10 +178,6 @@
     edx &= ~(1u << 30);
   }
 
-  // The SDBG bit is repurposed to denote AMD XOP support. Don't ever use AMD
-  // XOP code paths.
-  ecx &= ~(1u << 11);
-
   uint64_t xcr0 = 0;
   if (ecx & (1u << 27)) {
     // XCR0 may only be queried if the OSXSAVE bit is set.

crypto/internal.h

diff --git a/crypto/internal.h b/crypto/internal.h
index 960724e..0d9b0a6 100644
--- a/crypto/internal.h
+++ b/crypto/internal.h
@@ -1082,13 +1082,9 @@
 //
 //   Index 0:
 //     EDX for CPUID where EAX = 1
-//     Bit 20 is always zero
-//     Bit 28 is adjusted to reflect whether the data cache is shared between
-//       multiple logical cores
 //     Bit 30 is used to indicate an Intel CPU
 //   Index 1:
 //     ECX for CPUID where EAX = 1
-//     Bit 11 is used to indicate AMD XOP support, not SDBG
 //   Index 2:
 //     EBX for CPUID where EAX = 7, ECX = 0
 //     Bit 14 (for removed feature MPX) is used to indicate a preference for ymm
@@ -1100,7 +1096,7 @@
 // and AVX512 bits in XCR0, so it is not necessary to check those. (WARNING: See
 // caveats in cpu_intel.c.)
 //
-// From C, this symbol should only be accessed with |OPENSSL_get_ia32cap|.
+// This symbol should only be accessed with |OPENSSL_get_ia32cap|.
 extern uint32_t OPENSSL_ia32cap_P[4];
 
 // OPENSSL_get_ia32cap initializes the library if needed and returns the |idx|th