)]}'
{
  "commit": "1fcfbfd745168b6e6a1b2a78026edd8cef046ceb",
  "tree": "1972d2dde80aa5cbab572714a1e9511f92d9eeb9",
  "parents": [
    "d085e7bd13439f757651948727245476ee51f6b8"
  ],
  "author": {
    "name": "Rudolf Polzer",
    "email": "rpolzer@google.com",
    "time": "Thu May 21 00:38:34 2026 -0700"
  },
  "committer": {
    "name": "boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "email": "boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Tue Jun 02 07:29:55 2026 -0700"
  },
  "message": "For AES-GCM-SIV, also require PCLMUL instruction set.\n\nIt uses the VPCLMULQDQ instruction on XMM registers. This requires AVX\nand PCLMUL to be present.\n\nThe existing test checks for AVX, AESNI only, but not for PCLMUL.\n\nNote that there exist no CPUs that have AVX and AESNI, but lack PCLMUL,\nas both Intel and AMD introduced AESNI together with PCLMUL in the\nsame CPU generation. So this issue and fix is purely theoretical just in\ncase a future CPU for some odd reason has a weird combination of\nfeatures.\n\nChange-Id: I2cbcf8b5c165f4aba6e9b3127e6fc67d6a6a6964\nReviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/95667\nReviewed-by: Xiangfei Ding \u003cxfding@google.com\u003e\nCommit-Queue: Rudolf Polzer \u003crpolzer@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7c23bbb5be97f92af025d19c03302b17911c027b",
      "old_mode": 33188,
      "old_path": "crypto/cipher/e_aesgcmsiv.cc",
      "new_id": "47421fe9c7ebaa001a2f62fae39957fdfeb2a04f",
      "new_mode": 33188,
      "new_path": "crypto/cipher/e_aesgcmsiv.cc"
    }
  ]
}