)]}'
{
  "commit": "f5e0c8f92a22679b0cd8d24d0d670769c1cc07f3",
  "tree": "460beaa7d551e7213c802da9d3b2b4acd7f150a8",
  "parents": [
    "8a558aa2fc6172396a41e853cc5c6e3109a98f56"
  ],
  "author": {
    "name": "Brian Smith",
    "email": "brian@briansmith.org",
    "time": "Fri Dec 01 12:33:55 2023 -0800"
  },
  "committer": {
    "name": "Boringssl LUCI CQ",
    "email": "boringssl-scoped@luci-project-accounts.iam.gserviceaccount.com",
    "time": "Fri Jan 12 16:55:43 2024 +0000"
  },
  "message": "chacha: Move x86-64 CPU \u0026 length dispatching from assembly to C.\n\nThe x86-64 and x86 code both have 4x and 1x SSSE3 code paths. Only\nthe x86-64 version is modified here.\n\n(For 32-bit x86, it looks like it would be much harder to separate\nthe 1x and 4x code paths into separate functions and there\u0027s\nlittle motivation to do so. So it is likely that 32-bit x86 would\ndefine |CHACHA20_ASM_SSSE3| without |CHACHA20_ASM_SSSE3_4X|.)\n\nBug: 673\nChange-Id: I48a3fb8a2c6eb05a33c5ef20efff7ed000e51d71\nReviewed-on: https://boringssl-review.googlesource.com/c/boringssl/+/64467\nReviewed-by: Bob Beck \u003cbbe@google.com\u003e\nReviewed-by: David Benjamin \u003cdavidben@google.com\u003e\nCommit-Queue: David Benjamin \u003cdavidben@google.com\u003e\n",
  "tree_diff": [
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